A Arquitetura de Computadores
Por: Isabella Queiroz • 21/11/2021 • Trabalho acadêmico • 1.399 Palavras (6 Páginas) • 116 Visualizações
SOMADOR 1 BIT
library IEEE;
use IEEE.Std_Logic_1164.all;
entity somador is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end somador;
architecture Behavioral of somador is
begin
S <= (X xor Y xor Cin); Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end Behavioral;
SOMADOR 8 BITS
library IEEE;
use IEEE.Std_Logic_1164.all;
entity somador8bits is
Port ( busX : in STD_LOGIC_VECTOR (7 downto 0);
busY : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
busS : out STD_LOGIC_VECTOR (7 downto 0);
overflow: out STD_LOGIC);
end somador8bits;
architecture Behavioral of somador8bits is
COMPONENT somador
PORT(X : IN std_logic; Y : IN std_logic; Cin : IN std_logic; S : OUT std_logic;
Cout : OUT std_logic);
END COMPONENT;
SIGNAL C0 : std_logic;
SIGNAL C1 : std_logic;
SIGNAL C2 : std_logic;
SIGNAL C3 : std_logic;
SIGNAL C4 : std_logic;
SIGNAL C5 : std_logic;
SIGNAL C6 : std_logic;
SIGNAL C7 : std_logic;
begin
b0 : somador PORT MAP(
X => busX(0),
Y => busY(0),
Cin => Cin,
S => busS(0),
Cout => C0
);
b1 : somador PORT MAP(
X => busX(1),
Y => busY(1),
Cin => C0,
S => busS(1),
Cout => C1
);
b2 : somador PORT MAP(
X => busX(2),
Y => busY(2),
Cin => C1,
S => busS(2),
Cout => C2
);
b3 : somador PORT MAP(
X => busX(3),
Y => busY(3),
Cin => C2,
S => busS(3),
Cout => C3
);
b4 : somador PORT MAP(
X => busX(4),
Y => busY(4),
Cin => C3,
S => busS(4),
Cout => C4
);
b5 : somador PORT MAP(
X => busX(5),
Y => busY(5),
Cin => C4,
S => busS(5),
Cout => C5
);
b6 : somador PORT MAP(
X => busX(6),
Y => busY(6),
Cin => C5,
S => busS(6),
Cout => C6
);
b7 : somador PORT MAP(
X => busX(7),
Y => busY(7),
Cin => C6,
S => busS(7),
Cout => C7
);
overflow <= C6 XOR C7;
end Behavioral;
MUX
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux is
Port ( busX : in STD_LOGIC_VECTOR (7 downto 0);
busY : in STD_LOGIC_VECTOR (7 downto 0);
Sel : in STD_LOGIC;
busS : out STD_LOGIC_VECTOR (7 downto 0));
end mux;
architecture Behavioral of mux is
begin
busS <= busX when Sel = '0' else busY when Sel = '1';
end Behavioral;
INVERSOR
library IEEE;
use IEEE.Std_Logic_1164.all;
entity inversor is
Port ( busX : in STD_LOGIC_VECTOR (7 downto 0);
...